- Undisclosed
- Salary
- 15+ yrs
- Experience
- Full time
- Job type
Skills this role mentions
- Go
About the role
Job Description
The Role and Impact We are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel's bleeding FinFETs,GAA technologies. In this role, you will champion technical execution by overseeing compiler friendly and optimized floorplanning, high-density,performance based placement and routing template, and rigorous physical sign-off processes including DRC, LVS, Yield, DFM, Density, parasitic extraction, Noise Reliability i.e. EM, IR. You will provide technical guidance, set clear goals, and foster cross-functional collaboration with circuit design,…
Full details and the application are on Intel's careers site.
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